Implementation of Ultra Low Power Diode load based Gilbert cell Mixer for Wireless Applications

Transkripsi

1 IEEE INDICON Implementation of Ultra Low Power Diode load based Gilbert cell Mixer for Wireless Applications Priyanka, Alok Kumar Singh, Neeta Pandey 3,, 3 Department of Electronics and Communication Delhi Technological University Delhi, INDIA 508priyanka@gmail.com, aloksingh.dce@gmail.com, 3 neetapandey@dce.ac.in Abstract An Ultra Low Power Diode (ULPD) load based down conversion mixer is presented in this paper. The mixer is designed to operate at.5 GHz RF frequency with 50MHz Intermediate frequency. The conversion gain provided by the mixer is maximum ~8dB at.ghz RF frequency. The power consumption for the mixer core circuit is ~7mW. The mixer presents good RF to IF port isolation with input return loss less than zero. The Input Third Order Intercept increases from ~9dBm to 5.8 dbm for variation of the source degeneration inductors from nh to 0 nh. The IIP3 is.64dbm at 4 GHz RF frequency with nh inductor. The mixer is simulated with.8v voltage supply using 80nm CMOS process. The RF power is -30dBm and LO power is set to 5dBm. Keywords Conversion gain, linearity, down conversion, Gilbert Mixer, Ultra low power diode. I. INTRODUCTION The enormous growth in demand for handheld and wireless communication devices like cell phones, personal digital assistants (PDAs) has motivated researchers to develop RF circuits with enhanced performance on silicon IC. Although for radio frequency applications, integrated circuits realized by Bipolar and Gallium Arsenide technologies usually exhibit high performance, CMOS process is so exquisite because it substantially scales down the cost and complexity by implementing both analog and digital blocks of communication ICs. The advancement in CMOS technology has enabled the designing of integrated transceivers fulfilling all the consumer and commercial demands of portability, extended battery life (low power consumption due to minimized external components), high data rate and economical solutions for wireless communication. A mixer is the fundamental building block of CMOS receiver, which performs the task of frequency translation to a higher or lower spectrum for making the task of signal processing, easier and inexpensive. The designing and optimization of mixer requires a compromise between conversion gain, noise figure, port-to-port isolation, linearity, voltage scaling and power consumption. Fundamentally, mixers can be classified into active and passive with respect to their dc power consumption. Active mixers are capable of providing conversion gain that reduces noise contributed by the subsequent stages of the receiver. This conversion gain lowers the LO power required for their operation so they are widely used in RF applications. Passive mixers, on the other hand can operate at very high frequency (>0GHz) but always exhibit conversion loss rather than gain. In addition to excellent IM performance, they offer high linearity and fast switching but at the expense of LO power required. Passive mixers are therefore popular in microwave and base station circuits [4]. However, Large LO drive along with good LO-to-RF and LO-to-IF isolation is difficult to realize in low voltage and low power environments, therefore Active CMOS mixers are preferred to their passive counterpart in designing integrated circuitry. Various topologies of active mixer such as Single FET [5], Dual gate and Gilbert mixer (single and double balanced) [6] have been reported so far. Out of the various mixer topologies available, Gilbert cell topology has been extensively adopted for high performance IC applications. As compared to Single balanced topology, Double balanced mixer offers salient characteristics of higher linearity, port to port isolation, improved suppression of spurious gain products (symmetry leads to the suppression of even order products of LO / RF). In order to achieve these enhanced features at low voltage, several configurations have been proposed for the Double Balanced Gilbert mixer e.g. Current bleeding and Folded configuration. Using current bleeding approach, g m of the RF trans-conductance stage can be preserved while raising the value of load. However, this topology enhances conversion gain without affecting the power consumption, leakage currents also get introduced into the mixer circuit. These leakage currents are attributed by the parasitic capacitances of bleeding transistors. Parasitic capacitances not only constraints the bandwidth but also deteriorates the conversion gain by creating alternate path of signal leakage to the substrate ground. A folded cascode mixer structure can overcome the problem of voltage headroom of Gilbert mixer by eliminating stacked configuration of the transconductance and the switching stage /5/$ IEEE

2 but current consumption of this configuration becomes two times to that in the conventional Gilbert cell []. In this paper, a new type of active load for a CMOS Gilbert mixer is presented, which occupies considerably lesser area than the passive load while maintaining lower leakage current and power consumption. of the circuit increases again as in case of passive resistive load. Inductive and tuned loads are suitable for operation around a centre frequency so cannot be used for wideband operation. Among the various available loads, it has been observed that a PMOS load biased in the linear region gives better performance in terms of gain, linearity and area requirements. However, for setting a proper gate bias to get desired performance either an additional control voltage or extra circuitry is needed. In view of the different loads used in the used in Gilbert mixer, a new type of Active load called as ULPD (ultra low power diode) is presented here which not only provides higher and linearity but also consumess less power. Fig.. Basic Double Balanced Gilbert Mixer cell II. VARIOUS LOADS FOR MIXER Different types of loads have been reported in mixer designs e.g. passive resistor, simple PMOS transistor[], PMOS loads with certain other passive/active elements at its gate or forming a negative feedback path[7][8], current mirror, inductive load and RLC tuned load[3]. A. Ultra Low Power Diode Two configurations of diode using MOSFET transistors are shown in the figure below. Figure (a) shows the standard MOS diode with its gate and drain at same potential. If this diode is reverse-biased, the source of the MOS appears to be connected to the gate. The leakage current that flows is thus characterized by the drain current under the condition v gs = 0V and +V bs = -V D (where -ve sign shows the voltage applied to the diode when biased in reverse direction) []. This leakage current causes considerable increase in power consumption of the circuit. Although, increase in V th of the transistor can reduce the leakage current but will consequently lead to its poor forward drive capability. ULPD shown in fig.(b) consists of a combination of NMOS and PMOS transistors, in which gate of NMOS transistor is connected to the source of PMOS transistor and vice versa. When compared to standard MOS diodes, ULP diode has capability of reducing the leakage current strongly while maintaining the similar forward current drive. In CMOS technology, resistors with strictly controlled value and reasonable physical size are difficult to fabricate therefore, they are not preferred in modern designs. If passive load is replaced by an active load (i.e., load realized using MOSFETs), it can significantly reduce the required chip area as well as can yield higher gain for a mixer. The higher conversion gain with active load is achieved due to its higher small signal resistance []. Fig. (a) Standard MOS Diode (b) Ultra low power diode An active load can be implemented using diode connected MOS (i.e. gate of MOS transistor is connected to the drain of transistor). This configuration when used as load generally tends to achieve larger bandwidths but has lower gain because it has relatively lower value of output impedance. As an alternative load, Current mirror can provide higher gain (due to high output impedance) but at the expense of bandwidth []. When passive elements with PMOS load are used for enhancing gain or linearity, the power consumption and area When ULPD is in forward mode, it can be regarded as two forward biased standard NMOSFET and PMOSFET connected in series and therefore it has forward current comparable to that of a standard diode in reverse biased mode[]. As source terminal of NMOS and PMOS appears to be connected together as welll as both operate with negative voltages, their leakage current is small. It operates in moderate or weak inversion regions, depending upon the device thresholds. An important feature of ULPD is its ability to

3 serve as a resistor by operating the transistors in the linear region [4-6]. The equivalent impedance of ULPD at high frequencies for small input signal is given as- ended to differential) transformation at RF and LO inputs as well as for balanced to unbalanced transformation at the IF output terminals. Z () s R + sx As + Bs + C = As observed in above expression, the impedance of the ULPD load is a second order function with two poles and a zero. Where R and X denotes the real and imaginary parts of the zero of the impedance function respectively and A, B and C are the positive coefficients, which can be expressed as: R = r o + ro X = ( C + C )( r + r ) gd gd o o ( C + C )( C + C C )( A = + B = r + r gd gd gs gs gd o o ( Cgs + Cgs )( ro + ro ) + Cgdro ( + C r ( + g r ) gd o + gm ro gmro C = + m o + g m r Here r o and r o are drain source output resistances, m and g m are transconductances, C gs and C gs are gate source capacitances and C gd and C gd are the gate-drain capacitances of the NMOS and PMOS respectively. The additional zero introduced by the load enhances the bandwidth of the mixer. As observed in [] the leakage current remarkably reduces in ULPD, which for a MOS diode exists in nano-amperes range at zero V GS and dominates with back gate effect in reverse mode. ULPD finds applications in level keepers in MTCMOS circuits, charge pumps [3], memory cells [] etc. Here in this paper, it has been employed as load in Gilbert Mixer. ) o) g Fig.3 Proposed Gilbert Mixer with ULPD load IV. SIMULATION RESULTS The proposed down conversion Gilbert mixer is simulated using BSIM3 0.8µm RF CMOS process. The mixer is operated with a.8v supply voltage with an active current of 6mA. Fig.4 shows the variation of conversion gain with RF frequency. The positive conversion gain is obtained from 00MHz to 6 GHz with maximum value ~8dB at.ghz. The power consumption for the mixer core circuit ~7mW at.5 GHz operating frequency. The RF Input power is set to -30 dbm for simulation. III. ULPD LOAD BASED MIXER Fig. 3 shows the proposed Gilbert mixer with ULPD load. Gilbert mixer primarily encompassess three stages. Transconductance stage composed of transistors M 5 and M 6 functioning as the voltage to current conversion unit. The RF signal, which is to be down-converted, is applied to these transistors and hence two currents +I RF and I RF are produced for proper operation it should be ensured that M and M might not be steered into the saturation region [4]. Switching stage incorporates transistors M to M 4 multiplying the RF signal current to the LO signal applied. Load stage uses ULPDs comprising transistors (M 0, M ) and (M 9, M ) forming the two loads for the mixer. The linearity can be enhanced by adding degeneration resistors R and R. Baluns are the devices which are used for unbalanced to balanced (or single Fig.4 Conversion gain (db) versus RF frequency (Hz) with ULPD load 3

4 Fig.8 S (db) versus RF frequency (Hz) Fig.5 Input IP3 (dbm) versus RF frequency (Hz) Fig.9 S (db) versus RF frequency (Hz) Fig.6 Conversion gain (db) versus RF Power (dbm) In Fig.5, the variation of IIP3 with RF frequency is shown. The mixer achieves the input third order intercept as high as.64 db at 4GHz frequency and 4.85 db at 00 MHz Output IP3 has maximum value ~7.34 at 3.4GHz. From Fig.6, conversion gain is approximately constant up to - 0dBm with maximum value 7.8dB and then decreases. The LO power required for getting a specified conversion gain is shown in fig.7. Fig.8 and fig.9 shows the simulated Input RF port return loss and RF-IFF port isolation as a function of frequency. S obtained is lesss than 0db and S is less than -450 db for the entire frequency range of operation. The linearity of the mixer is enhanced by using the source degeneration inductors in the transconductance stage. Table I depicts the variation of conversion gain, IIP3 and OIP3 with the value of these inductors. It is observed that linearity of the mixer increases and the corresponding gain decreases as we increase the value of inductor nh to 5nH because of the tradeoffs involved between the Conversion gain and the linearity. However, there is a limit up to which Ls can be increased for linearity enhancement. TABLE I. MIXER PARAMETERS FOR DIFFERENT INDUCTOR (L S) VALUES (AT.5 GHZ RF FREQUENCY) Fig.7 Conversion gain (db) versus LO Power (dbm) Conversion Ls(nH) Gain (db) Input Intercept Point (dbm) Output Intercept Point (dbm)

5 TABLE II: PERFORMANCE COMPARISON WITH OTHER REPORTED PAPERS References Parameters CMOS Technology (µm) This work CG (db) 7.97 RF freq (GHz) Core Mixer Power (mw) [7] [8] [9] [0] [] S (db) < 0 < - - < IIP3 (dbm) V DD (V) V. CONCLUSION The ULPD load presented here, reduces the leakage power and hence the power consumption for the Mixer. By operating the diode in the linear region, Gilbert mixer with reasonably high linearity and adequately large conversion gain can be designed. Besides this, ULPD enhances the bandwidth of the mixer also. The comparison of proposed mixer with other implemented mixers is shown in Table II. However, this mixer has a voltage headroom limitation but by utilizing emerging multi-vth (Threshold voltage) fully SOI (Silicon on Insulator) CMOS process, sufficiently low voltage operation can be achieved []. [7] Chih-Hau Chen and Christina.F Jou, A 3-8GHz Broadband Low Power Mixer, Piers Online, vol.4, no.3, pp , 008. [8] Hu Zijie, Koen Mouthaan, A - to 0-GHz RF and Wideband IF Cross-Coupled Gilbert Mixer in 0.3-μm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no., 03. [9] Ming Da Tsai, Huei Wang, A GHz Ultra WidebandMixer Using Commercial 0.8µm CMOS Technology, IEEE Microwave and Wireless Components letters, vol.4, no., pp. 5-54, 004. [0] Vojkan Vidojkovic, Johan vander Tang, Arjan Leeuwenburgh and Arthur H.M. van Roermund, A Low Voltage Folded-Switching Mixer in 0.8 µm CMOS, IEEE Journal of Solid-State circuits, vol.40, no.6, pp , 005. [] Tuan-Anh Phan, Chang-Wan Kim, and Sang-Gug Lee, T.-J. Park, E.-J. Kim, Gain Mismatch-Balanced I/Q Down-Conversion Mixer for UWB, IEEE conference on Circuits and Systems(ISCAS) pp , 006. [] Tony Chan Carusone, David A.Johns, Kenneth W.Martin, Analog Integrateds Circuits Design,John Wiley & sons, second Edition. [3] D. Levacq, C. Liber, V. Dessard, Ultra Low Power design techniques using specisl SOI MOS Diodes, IEEE International conference on SOI, pp. 9-0, 003. [4] P. J. Sullivan, B. A. Xavier and W. H. Ku, Low Voltage Performance of a Microwave CMOS Gilbert Cell Mixer IEEE Journal of Solid-State circuits, vol. 3, no. 7, 997. [5] F. Giannini, G. Leuzzi, Nonlinear Microwave Circuit Design, John Wiley & Sons, 004. [6] S.A. Maas. Nonlinear microwave circuits and RF design, Norwood MA: Artech House, 003. [7] Mostafa Yargholi, Farsha Darvishi, A low-voltage high-linearity UWB down-conversion mixer in 0.8µm Technology, nd Iranian conference on Electrical Engineering(ICEE ), 04. [8] Mahdi Parvizi, A. nabavi, Low voltage highly linear UWB CMOS Mixer with simultaneous second and third order distortion cancellation, Microelectronics journal, issue 4, pp.-8, 00. [9] Man Long Her, Chun-Yuan Huang, Pao-Hsun Wu, A Gilbert Mixer with high gain for 8 GHz application, Cross Strait Quad- Regional Radio Science and Wireless Technology Conference, 0. REFERENCES [] D. Levacq, C. Liber, V. Dessard, D. Flandre, Composite ULP diode fabrication.modelling and applications in multi-vth FD SOI CMOS technology, Solid-State Electronics,vol.48,pp , 004. [] R. Salmeh, Analysis Of The Effects Of The Load On The Gain, Linearity And Noise Figure Of A Gilbert Cell double Balannced Mixer, IEEE Conference of Circuits and Systems, vol.,pp , 006. [3] K. Munusamy, Z. Yusoff, A Highly Linear CMOS Down Conversion Double Balanced Mixer IEEE International Conference on Semiconductor Electronics, pp , 006. [4] N. Kumar Babu, P. Sasibala, Fast Low Power Frequency Synthesis Applications by Using A DCVSL Delay Cell, International Journal of Electrical and Electronics Engineering(IJEEE), ISSN(Print) 3-584, vol.3, Issue-, 03. [5] D. Z. Turker, S. Khatri, E. Sanchez-Sinencio, A DCVSL Cell for Fat Low Power Frequency Synthesis Applications, IEEE Journal and Magazines, vol.58, Issue 6, pp. 5-38, 0. [6] A. Srinivasulu and M. Rjesh, UPLD and CPTL pull-up satges for Differntial Cascode Voltage Switch Logic, Hindwai publishing corporation, Journal of Engineering, vol.03, Article ID 59596, 03. 5