PROSESOR: CONTROL DAN DATAPATH. Oky Dwi Nurhayati, ST, MT

Transkripsi

1 PROSESOR: CONTROL DAN DATAPATH Oky Dwi Nurhayati, ST, MT 1

2 Prosesor: Control & Datapath Computer Processor (active) Control ( brain ) Datapath ( brawn ) Memory (passive) (where programs, data live when running) Devices Input Output 2

3 Organisasi Prosesor (Singlebus) Control Memory bus Address Data PC MAR MDR Instruction Decoder IR R0 Control Unit Y control Add Sub XOR Carry-in R(n-1) Datapath Unit Z TEMP 3

4 Siklus Eksekusi Instruksi Eksekusi instruksi yang ukurannya tetap do { 1. IR M[PC] // Fetch instruksi 2. PC PC + d // Tunjuk ke lokasi instruksi berikutnya 3. Eksekusi instruksi } while (!stop) Eksekusi instruksi yang ukurannya bervariasi do { do { // Fetch instruksi IR M[PC] PC PC + d } while (!end-of-instruction) Eksekusi instruksi } while (!stop) 4

5 Operasi-operasi Dasar & Waktu Eksekusi Operasi-operasi Dasar: Mengambil (fetching) Data dari Memori Menyimpan (storing) Data ke Memori Pertukaran Data Antar-Register Operasi Aritmatika & Logika di Datapath Waktu Eksekusi Gate Delay - Waktu yang dibutuhkan output suatu gerbang logika berubah sesuai kondisi inputnya Register s Delay - Waktu yang dibutuhkan isi register berubah sesuai inputnya 5

6 Mengambil Data dari Memori Instruksi: Read MFC LD R2,(R1) ; R2 M[R1] PC Instruction Decoder Langkah-langkah: MAR R1 Read Address Data MAR MDR IR R1 Tunggu sinyal MFC // MFC = Memory Function Completed // Pada saat MFC aktif: // MDR M[MAR] R2 MDR Add Sub XOR Y Carry-in R2 Z TEMP 6

7 Menyimpan Data ke Memori Instruksi: Write MFC ST (R1),R2 ; M[R1] R2 PC Instruction Decoder Langkah-langkah: MAR R1 MDR R2, Write Address Data MAR MDR IR R1 Tunggu sinyal MFC // MFC = Memory Function Completed // Pada saat MFC aktif: // M[MAR] MDR Add Sub XOR Y Carry-in R2 Z TEMP 7

8 Pengendalian Transfer Data Dari/Ke Register 8

9 Pertukaran Data Antar-Register: Input & Output Gating 1 bit line of common bus S Q R Z in Operasi Tulis 1-bit bus Z in Q X 0 Q operasi tulis & baca dilakukan secara bergantian _ Q Z out Operasi Baca Z out Q output 0 X 3-state output: 1, 0, open-circuit 3-state switch memungkinkan peranti lain menggunakan bus 9

10 Pertukaran Data Antar-Register R1 in X Instruksi: MOV R4,R1 ; R4 R1 R1 R1 out R4 in X X Langkah-langkah: Enable output of R1 // setting R1 out to 1 Enable input of R4 // setting R4 in to 1 R4 X R4 out 10

11 Operasi Aritmatika dan Logika Ri Ri in X X Instruksi: ADD R1,R2 ; R1 R1 + R2 Y Ri out Y in Y out X X Langkah-langkah: R1 out, Y in R2 out, Add, Z in Z out, R1 in A B Add X Z in Z X Z out 11

12 Waktu Eksekusi 12

13 Waktu Eksekusi: Gate Delay When input 0 1, output 1 0 but NOT instantly Output goes 1 0: output voltage goes from Vdd (5v) to 0v When input 1 0, output 0 1 but NOT instantly Output goes 0 1: output voltage goes from 0v to Vdd (5v) Voltage does not like to change instantaneously Voltage 1 => Vdd Vout In Out Vin 0 => GND Time 13

14 Waktu Eksekusi: Series Connection Vin V1 Vout Vdd Vdd Voltage Vdd G1 G2 Vin G1 V1 G2 C1 Vin V1 Vout Vout Cout Vdd/2 d1 d2 GND Total Propagation Delay = Sum of individual delays = d1 + d2 Capacitance C1 has two components: Capacitance of the wire connecting the two gates Input capacitance of the second inverter Time 14

15 Waktu Eksekusi: Register s Delay Clk D Q Setup Hold D Don t Care Don t Care Clk Q Unknown Clock-to-Q Setup Time: Input must be stable BEFORE the trigger clock edge Hold Time: Input must REMAIN stable after the trigger clock edge Clock-to-Q time: Output cannot change instantaneously at the trigger clock edge 15

16 Waktu Eksekusi Ri in X R2 out, Add, Z in Turn-on time for 3-state driver Ri Ri out Y in X X Transmission time Y X Propagation delay through Y out A B Add X Z in Setup time Z Hold time X Z out 16

17 Langkah-langkah Pengeksekusian Instruksi 17

18 Operasi (A&L): Bagian dari Pertukaran Data Komponen-komponen Datapath: Register: tempat penyimpanan data : tempat pemrosesan aritmatika & logika Bus: penghubung antar-register & antara register- Eksekusi Instruksi merupakan kombinasi pertukaran data antara: Register Bus Register Register Bus Register Bus Memori Pertukaran data dilakukan dengan cara mengaktifkan gerbang-gerbang register dengan menggunakan sinyal-sinyal kendali (PC out, PC in, dst.) Selain itu, juga ada sinyal-sinyal kendali yang berhubungan dengan komponen-komponen lain (Memori: Read, Write; : Add, Sub, Set Carry-in, dst.) 18

19 Tahapan Eksekusi Instruksi Instruksi: Add R1,(R3) ; R1 R1 + M[R3] Langkah-langkah: 3. Fetch instruksi PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC MDR out, IR in 4. Fetch operand #1 (isi lokasi memori yg ditunjuk oleh R3) R3 out, Read R1 out, Y in, WMFC 5. Lakukan operasi penjumlahan MDR out, Add, Z in 6. Simpan hasil penjumlahan di R1 Z out, R1 in, End 19

20 1. Fetch instruksi PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in Address PC MAR Instruction Decoder IR Data MDR R1 Add Y PC+1 Z 1 Carry-in R3 TEMP 20

21 2. Fetch operand #1 R3 out, Read R1 out, Y in, WMFC Address Data PC=PC+1 MAR MDR Instruction Decoder IR R1 Y R3 Z TEMP 21

22 3. Lakukan operasi penjumlahan MDR out, Add, Z in Address Data PC=PC+1 MAR MDR=M[R3] Instruction Decoder IR R1 Add Y=R1 R3 Carry-in Z in Z TEMP 22

23 4. Simpan hasil penjumlahan Z out, R1 in, End Address Data PC=PC+1 MAR MDR=M[R3] Instruction Decoder IR R1 Y=R1 R3 Z=R1+M[R3] TEMP 23

24 Tahapan Eksekusi Branching Unconditional (JMP Loop) PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC MDR out, IR in PC out, Y in Offset-field-of-IR out, Add, Z in // PC PC + Offset Z out, PC in, End Conditional (contoh: BRNeg Loop) PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC MDR out, IR in PC out, Y in, If N=0 then End // take the branch? Offset-field-of-IR out, Add, Z in // PC PC + Offset Z out, PC in, End 24

25 LD R d,x 25

26 Tahapan Eksekusi Instruksi: LD R d,x Instruksi: LD R16,X ; R16 M[X] Langkah-langkah: 3. Fetch instruksi PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC MDR out, IR in 4. Fetch operand dari lokasi memori yang ditunjuk oleh X X out, Read WMFC Lakukan operasi Simpan hasil penjumlahan di R16 MDR out, R16 in, End 26

27 Tahapan Eksekusi Instruksi: LD R d,x PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Read Control MDR out, IR in X out, Read WMFC MDR out, R16 in, End Address Data PC PC out MAR MAR in MDR Instruction Decoder IR X Clear Y Y Add R16 Z PC+1 1 Set Carry-in TEMP Z in 27

28 Tahapan Eksekusi Instruksi: LD R d,x PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control WMFC MDR out, IR in X out, Read WMFC MDR out, R16 in, End Address Data PC PC in MAR MDR Instruction Decoder IR X Y R16 Z = PC+1 TEMP Z out 28

29 Tahapan Eksekusi Instruksi: LD R d,x PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in X out, Read WMFC MDR out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR IR in X MDR out Y R16 Z TEMP 29

30 Tahapan Eksekusi Instruksi: LD R d,x PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Read Control MDR out, IR in X out, Read WMFC MDR out, R16 in, End Address Data PC+1 MAR MAR in MDR Instruction Decoder IR X Y X out R16 Z TEMP 30

31 Tahapan Eksekusi Instruksi: LD R d,x PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control WMFC MDR out, IR in X out, Read WMFC MDR out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR X Y R16 Z TEMP 31

32 Tahapan Eksekusi Instruksi: LD R d,x PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in X out, Read WMFC MDR out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR X MDR out Y R16 R16 in Z TEMP 32

33 ADD R d,r s 33

34 Tahapan Eksekusi Instruksi: ADD R d, R s Instruksi: ADD R16,R17 ; R16 R16 + R17 Langkah-langkah: 3. Fetch instruksi PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC MDR out, IR in 4. Fetch operand ke-1 (R16) R16 out, Y in 5. Fetch operand ke-2 (R17) dan Lakukan operasi R17 out, Add, Z in 6. Simpan hasil penjumlahan di R16 Z out, R16 in, End 34

35 Tahapan Eksekusi Instruksi: ADD R d, R s PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Read Control MDR out, IR in R16 out, Y in R17 out, Add, Z in Z out, R16 in, End Address Data PC PC out MAR MAR in MDR Instruction Decoder IR R17 Clear Y Y Add R16 Z PC+1 1 Set Carry-in TEMP Z in 35

36 Tahapan Eksekusi Instruksi: ADD R d, R s PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control WMFC MDR out, IR in R16 out, Y in R17 out, Add, Z in Z out, R16 in, End Address Data PC PC in MAR MDR Instruction Decoder IR R17 Y R16 Z = PC+1 TEMP Z out 36

37 Tahapan Eksekusi Instruksi: ADD R d, R s PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in R16 out, Y in R17 out, Add, Z in Z out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR IR in R17 MDR out Y R16 Z TEMP 37

38 Tahapan Eksekusi Instruksi: ADD R d, R s PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in R16 out, Y in R17 out, Add, Z in Z out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR R17 Y in Y R16 R16 out Z TEMP 38

39 Tahapan Eksekusi Instruksi: ADD R d, R s PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in R16 out, Y in R17 out, Add, Z in Z out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR R17 Y=R16 R17 out R16 Add Z in Z TEMP 39

40 Tahapan Eksekusi Instruksi: ADD R d, R s PC out, Read, Clear Y, Set carry-in to, Add, Z in Z out, PC in, WMFC Control MDR out, IR in R16 out, Y in R17 out, Add, Z in Z out, R16 in, End Address Data PC+1 MAR MDR Instruction Decoder IR R17 Y=R16 R16 R16 out Z out Z=R16+R17 TEMP 40

41 Peningkatan Kinerja Prosesor 41

42 Multiple-bus: salah satu cara peningkatan kinerja A B C Instruction Decoder IR PC Register File TEMP Add R1,R2,R3 ;R1 R2+R3 MDR MAR Data Address Memory Bus 42

43 Bandingkan dengan Organisasi Singlebus PC Instruction Decoder MAR IR MDR Y R1 R2 R3 Add R1,R2,R3 ;R1 R2+R3 Z TEMP 43

44 Beberapa Teknik Peningkatan Kinerja Prosesor Lainnya Pre-fetching: instruksi berikutnya (i+1) di-fetch pada waktu pengeksekusian instruksi (i) Perlu teknik Branch Prediction Pipelining: eksekusi instruksi dipecah kedalam tahap-tahap yang dapat dilakukan secara overlap Fetch Instruksi Decode Instruksi Baca Operand (dari register asal) Lakukan Operasi Tulis Hasil (ke register tujuan) On-chip Cache: mempercepat akses data dari/ke memori 44

45 Arsitektur Intel P6 (Pentium Pro) 45

46 Arsitektur SPARCstation20 TI SuperSPARC tm TMS390Z50 in Sun SPARCstation20 SuperSPARC MBus Module Floating-point Unit Integer Unit L2 $ CC MBus DRAM Controller Inst Cache Ref MMU Bus Interface Data Cache Store Buffer L64852 SBus SBus DMA SBus Cards MBus control M-S Adapter SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy 46